Problem 5-42

entity Prob5-42 is

    port(A, B, C, D: in bit; X: out bit);

end entity Prob5-42;

architecture Function5-42 of Prob5-42 is

begin

    X <= not ((not A and B) or (not A and C and D));

end architecture Function5-42;

Problem 5-44

entity Prob5-44 is

    port(A, B, C, D: in bit; X: out bit);

end entity Prob5-44;

architecture Function 5-44 of Prob5-44 is

component NOT_Gate is

    port(A: in bit; X: out bit);

end component NOT_Gate;

component NOR_Gate is

    port(A, B: in bit; X: out bit);

end component NOR_Gate;

component NAND_Gate is

    port(A, B: in bit; Z: out bit);

end component NAND_Gate;

signal x1, x2, x3, x4, x5: bit;

begin

    G1: NOT_Gate port map(A=>A, X=>x1);

    G2: NOR_Gate port map(A=>x1, B=>B, X=>x2);

    G3: NAND_Gate port map(A=>B, B=>C, X=>x3);

    G4: NAND_Gate port map(A=>x2, B=>x3, X=>x4);

    G5: NOR_Gate port map(A=>x4, B=>D, X=>x5);

    G6: NOT_Gate port map(A=>x5, X=>X);

end architecture Function_5-44;